1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to capacitor structures having increased capacitance that can be used as charge storage elements for various memory cells including dynamic random access memory (DRAM) cells. The present invention also relates to methods of fabricating such capacitor structures for use in various memory cells.
2. Background of the Invention
A memory cell in an integrated circuit (IC) includes a transfer device such as a transistor and an associated capacitor. The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of ICs with memory cells is increased, the area for the capacitor becomes smaller and the amount of charge the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
Dynamic random access memory (DRAM) cells are widely used in storing information because they can be implemented to provide an extraordinary number of memory cells in a relatively small area. Although various techniques are known for fabricating DRAM cells, planar DRAM processes have the benefit of low cost and easy integration with standard complementary metal oxide semiconductor (CMOS) processing. The major problem associated with planar capacitors is the inability to scale with technology generations. As cell sizes have decreased, the planar capacitor has not scaled accordingly due to tunneling current constraints. The gate dielectric thickness tends to be 2–3 generations behind. Therefore, to keep the cell capacitance high, the area of the planar capacitor cannot scale with the technology and thus dominates cell area.
One attempt to reduce the cell area, as well as the integration area required for each cell is disclosed, for example, in U.S. Pat. No. 6,087,214 to Cunningham. Specifically, the Cunningham disclosure provides a method for fabricating a memory cell which includes the steps of: selectively removing portions of a substrate using a patterned mask to simultaneously form a capacitor trench and an isolation trench which is at least partially around the capacitor trench; forming an oxide in both the isolation and capacitor trenches; selectively removing the oxide in the capacitor trench; doping portions of substrate so as to define the base and sidewalls of the capacitor; forming a thin capacitor dielectric on the exposed walls (including bottom and sidewalls) of the capacitor trench; and then filling the remaining portion of the capacitor trench with polysilicon.
Despite creating more cell capacitance, the process and structure disclosed in the Cunningham disclosure suffer an area penalty because an isolation trench is needed around the to provide cell-to-cell isolation. No method or structure is provided in the Cunningham disclosure that eliminates the isolation trench around the memory cell. As such, the process and structure disclosed in Cunningham fails to provide a capacitor structure for a memory cell having the combination of high cell capacitance and reduced cell area.
In view of the drawbacks mentioned above with prior art processes of fabricating memory cells having the combination of high cell capacitance and reduced cell area, there exists a need for providing a new and improved method for fabricating such memory cells.